W3H128M72E-XSBX / W3H128M72E-XNBX
DDR2 ICC SPECIFICATIONS AND CONDITIONS
667
CL6
533
CL5
400
CL4
Symbol
Proposed Conditions
Units
Operating one bank active-precharge current;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC0
t
675
800
55
575
675
55
575
675
55
mA
Operating one bank active-read-precharge current;
ICC1
ICC2P
ICC2Q
ICC2N
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is
mA
mA
mA
mA
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
325
350
225
300
200
250
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
200
50
175
50
150
50
mA
mA
ICC3P
Active standby current;
ICC3N
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
375
275
950
250
800
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC4W
1,250
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as IDAD6W
ICC4R
1,375
975
900
mA
Burst auto refresh current;
ICC5
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,400
45
1,300
45
1,250
45
mA
mA
Self refresh current;
ICC6
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC),
RRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
ICC7
t
1,975
1,775
1,775
mA
are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing
conditions
22
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
