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W3H128M72E-400NBM 参数 Datasheet PDF下载

W3H128M72E-400NBM图片预览
型号: W3H128M72E-400NBM
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX72, 1.35ns, CMOS, PBGA208, BGA-208]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 31 页 / 1024 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
 浏览型号W3H128M72E-400NBM的Datasheet PDF文件第20页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第21页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第22页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第23页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第25页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第26页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第27页浏览型号W3H128M72E-400NBM的Datasheet PDF文件第28页  
W3H128M72E-XSBX / W3H128M72E-XNBX  
AC TIMING PARAMETERS (continued)  
667Mbs CL6  
533Mbs CL5  
400Mbs CL4  
Min Max  
Parameter  
DQ hold skew factor  
Symbol  
Unit  
Min  
-
Max  
400  
Min  
-
Max  
400  
tQHS  
tAC  
-
450  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
DQ output access time from CK/CK#  
Data-out high impedance window from CK/CK#  
DQS Low-Z window from CK/CK#  
DQ Low-Z window from CK/CK#  
-100  
1,250  
-100  
1,350  
-100  
1,350  
tHZ  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
1
tLZ  
tAC(MN)  
2*tAC(MN)  
400  
tAC(MN)  
2*tAC(MN)  
400  
tAC(MN)  
2*tAC(MN)  
400  
2
tLZ  
tDSa  
tDHa  
tDSb  
tDHb  
tDIPW  
tQHS  
350  
350  
400  
DQ and DM input setup time relative to DQS  
100  
100  
150  
225  
225  
275  
DQ and DM input pulse width (for each input)  
Data hold skew factor  
0.35  
0.35  
0.35  
400  
400  
450  
DQ-DQS hold, DQS to rst DQ to go nonvalid, per  
access  
tQH  
tHP - tQHS  
tHP - tQHS  
tHP - tQHS  
ps  
Data valid output window (DVW)  
DQS input high pulse width  
tDVW  
tDQSH  
tDQSL  
tDQSCK  
tDSS  
tQH - tDQSQ  
0.35*tCK  
0.35*tCK  
-100  
tQH - tDQSQ  
0.35*tCK  
0.35*tCK  
-100  
tQH - tDQSQ  
0.35*tCK  
0.35*tCK  
-100  
ns  
tCK  
tCK  
ps  
DQS input low pulse width  
DQS output access time fromCK/CK#  
DQS falling edge to CK rising - setup time  
DQS falling edge from CK rising - hold time  
1,250  
240  
1,350  
300  
1,350  
350  
0.2*tCK  
0.2*tCK  
0.2*tCK  
0.2*tCK  
0.2*tCK  
0.2*tCK  
tCK  
tCK  
tDSH  
DQS-DQ skew, DOS to last DQ valid, per group, per  
access  
tDQSQ  
ps  
DQS read preamble  
tRPRE  
tRPST  
0.9*tCK  
0.4*tCK  
0
1.1*tCK  
0.6*tCK  
0.9*tCK  
0.4*tCK  
0
1.1*tCK  
0.6*tCK  
0.9*tCK  
0.4*tCK  
0
1.1*tCK  
0.6*tCK  
tCK  
tCK  
ps  
DQS read postamble  
DQS write preamble setup time  
tWPRES  
DQS write preamble  
tWPRE  
0.35*tCK  
0.25*tCK  
0.25  
tCK  
DQS write postamble  
tWPST  
tDQSS  
0.4*tCK  
-0.25*tCK  
WL-TDQSS  
0.6*tCK  
0.25*tCK  
0.4*tCK  
-0.25*tCK  
WL-TDQSS  
0.6*tCK  
0.25*tCK  
0.4*tCK  
-0.25*tCK  
WL-TDQSS  
0.6*tCK  
0.25*tCK  
tCK  
tCK  
tCK  
Positive DQS latching edge to associated clock edge  
Write command to rst DQS latching transition  
WL+TDQSS  
WL+TDQSS  
WL+TDQSS  
24  
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX  
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com  
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