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MX25L1635DMI-12G 参数 Datasheet PDF下载

MX25L1635DMI-12G图片预览
型号: MX25L1635DMI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ ×1 / ×2 / ×4 ] CMOS串行闪存 [16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 50 页 / 728 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25L1635D  
HardwareProtectedMode(HPM):  
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When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware  
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1,  
BP0 and hardware protected mode by the WP#/SIO2 to against data modification.  
Note:  
ToexitthehardwareprotectedmoderequiresWP#/SIO2drivinghighoncethehardwareprotectedmodeisentered.Ifthe  
WP#/SIO2pinispermanentlyconnectedtohigh,thehardwareprotectedmodecanneverbeentered;onlycanusesoftware  
protected mode via BP3, BP2, BP1, BP0.  
If the system goes into four I/O read mode, the feature of HPM will be disabled.  
(6)ReadDataBytes(READ)  
Thereadinstructionisforreadingdataout.TheaddressislatchedonrisingedgeofSCLK,anddatashiftsoutonthefalling  
edgeofSCLKatamaximumfrequencyfR.Thefirstaddresscanbeatanylocation.Theaddressisautomaticallyincreased  
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ  
instruction. The address counter rolls over to 0 when the highest address has been reached.  
The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI  
-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure 14)  
(7)ReadDataBytesatHigherSpeed(FAST_READ)  
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of  
each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address can be at any location. The  
address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory  
can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has  
beenreached.  
The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte  
address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at  
any time during data out. (see Figure 15)  
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact  
on the Program/Erase/Write Status Register current cycle.  
(8) 2 x I/O Read Mode (2READ)  
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of  
SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency  
fT. The first address can be at any location. The address is automatically increased to the next higher address after each  
byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls  
overto0whenthehighestaddresshasbeenreached.Oncewriting2READinstruction,thefollowingaddress/dummy/data  
out will perform as 2-bit instead of previous 1-bit.  
The sequence of issuing 2READ instruction is: CS# goes lowsending 2READ instruction24-bit address interleave  
on SIO1 & SIO04 dummy cycles on SIO1 & SIO0data out interleave on SIO1 & SIO0to end 2READ operation  
can use CS# to high at any time during data out (see Figure 16 for 2 x I/O Read Mode Timing Waveform).  
WhileProgram/Erase/WriteStatusRegistercycleisinprogress, 2READinstructionisrejectedwithoutanyimpactonthe  
Program/Erase/Write Status Register current cycle.  
P/N:PM1374  
REV. 1.5, OCT. 01, 2008  
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