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MX25L1635DMI-12G 参数 Datasheet PDF下载

MX25L1635DMI-12G图片预览
型号: MX25L1635DMI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ ×1 / ×2 / ×4 ] CMOS串行闪存 [16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 50 页 / 728 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25L1635D  
(4)ReadStatusRegister(RDSR)  
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in  
program/erase/writestatusregistercondition)andcontinuously. ItisrecommendedtochecktheWriteinProgress(WIP)  
bit before sending a new instruction when a program, erase, or write status register operation is in progress.  
ThesequenceofissuingRDSRinstructionis:CS#goeslow->sendingRDSRinstructioncode->StatusRegisterdataout  
on SO (see Figure 12)  
The definition of the status register bits is as below:  
WIP bit. TheWriteinProgress(WIP)bit, avolatilebit, indicateswhetherthedeviceisbusyinprogram/erase/writestatus  
registerprogress.WhenWIPbitsetsto1,whichmeansthedeviceisbusyinprogram/erase/writestatusregisterprogress.  
When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.  
WELbit.TheWriteEnableLatch(WEL)bit, avolatilebit, indicateswhetherthedeviceissettointernalwriteenablelatch.  
When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write  
status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept  
program/erase/writestatusregisterinstruction.Theprogram/erasecommandwillbeignoredandnotaffectvalueofWEL  
bit if it is applied to a protected memory area.  
BP3, BP2, BP1, BP0bits. TheBlockProtect(BP3, BP2, BP1, BP0)bits, non-volatilebits, indicatetheprotectedarea(as  
defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To  
write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed.  
Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE)  
and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).  
QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP#  
or is set to "1" to enable Quad SIO2 and SIO3.  
SRWDbit.TheStatusRegisterWriteDisable(SRWD)bit,non-volatilebit,whichissetto"0"(factorydefault).TheSRWD  
bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware  
protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the  
Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits  
(BP3, BP2, BP1, BP0) are read only.  
StatusRegister  
bit7  
SRWD  
(status register  
write protect)  
bit6  
bit5  
BP3  
(level of  
bit4  
BP2  
(level of  
bit3  
BP1  
(level of  
bit2  
BP0  
(level of  
bit1  
WEL  
(write enable  
bit0  
WIP  
(write in  
progress bit)  
1= write  
operation  
QE  
(Quad Enable)  
protected block) protected block) protected block) protected block)  
latch)  
1= Quad  
Enable  
1= status  
register write  
disable  
1= write enable  
0= not write  
enable  
(note1)  
(note1)  
(note1)  
(note1)  
0=not Quad  
Enable  
0= not in write  
operation  
Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit  
volatile bit  
volatile bit  
Note 1: see the table 2 "Protected Area Size" in page 11.  
P/N:PM1374  
REV. 1.5, OCT. 01, 2008  
16