MX25L1635D
(1)WriteEnable(WREN)
TheWriteEnable(WREN)instructionisforsettingWriteEnableLatch(WEL)bit. ForthoseinstructionslikePP, 4PP, CP,
SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN
instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see
Figure9)
(2)WriteDisable(WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
ThesequenceofissuingWRDIinstructionis:CS#goeslow->sendingWRDIinstructioncode->CS#goeshigh.(seeFigure
10)
The WEL bit is reset by following situations:
-Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Quad Page Program (4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
- Continuously program mode (CP) instruction completion
(3)ReadIdentification(RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 24(hex) as the first-byte device ID, and the individual device ID of
second-byte ID are listed as table of "ID Definitions". (see table 7 in page 26)
ThesequenceofissuingRDIDinstructionis:CS#goeslow->sendingRDIDinstructioncode->24-bitsIDdataoutonSO
-> to end RDID operation can use CS# to high at any time during data out. (see Figure 11.)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of
program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N:PM1374
REV. 1.5, OCT. 01, 2008
15
Macronix [ MACRONIX INTERNATIONAL ]
