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MX25L1635DMI-12G 参数 Datasheet PDF下载

MX25L1635DMI-12G图片预览
型号: MX25L1635DMI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ ×1 / ×2 / ×4 ] CMOS串行闪存 [16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 50 页 / 728 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25L1635D  
sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction.  
The CS# must go high exactly at the byte boundary (the eighth bit of address byte been latched-in); otherwise, the  
instruction will be rejected and not executed.  
The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#  
goes high. (see Figure 23)  
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress  
(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and  
sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by  
BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.  
(12) Chip Erase (CE)  
TheChipErase(CE)instructionisforerasingthedataofthewholechiptobe"1".AWriteEnable(WREN)instructionmust  
execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at  
the byte boundary (the eighth bit of address byte been latched-in), otherwise the instruction will be rejected and not  
executed.  
The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure  
24)  
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress  
(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and  
sets0whenChipEraseCycleiscompleted, andtheWriteEnableLatch(WEL)bitisreset. Ifthechipisprotectedby BP3,  
BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1,  
BP0 all set to "0".  
(13) Page Program (PP)  
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must  
execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the  
last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least  
significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted  
datagoingbeyondtheendofthecurrentpageareprogrammedfromthestartaddressofthesamepage(fromtheaddress  
A7-A0areall0). Ifmorethan256bytesaresenttothedevice, thedataofthelast256-byteisprogrammedattherequest  
page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the  
requested address of the page without effect on other address of the same page.  
ThesequenceofissuingPPinstructionis:CS#goeslow->sendingPPinstructioncode->3-byteaddressonSI->atleast  
1-byte on data on SI-> CS# goes high. (see Figure 19)  
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary(  
the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.  
Theself-timedPageProgramCycletime(tPP)isinitiatedassoonasChipSelect(CS#)goeshigh. TheWriteinProgress  
(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and  
sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected  
by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.  
P/N:PM1374  
REV. 1.5, OCT. 01, 2008  
20