MX25L1635D
(14) 4 x I/O Page Program (4PP)
TheQuadPageProgram(4PP)instructionisforprogrammingthememorytobe"0". AWriteEnable(WREN)instruction
must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the
QuadPageProgram(4PP). TheQuadPageProgrammingtakesfourpins:SIO0, SIO1, SIO2, andSIO3asaddressand
datainput,whichcanimproveprogramerperformanceandtheeffectivenessofapplicationoflowerclocklessthan20MHz.
For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal
page program time is far more than the time data flows in. Therefore, we suggest that while executing this command
(especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions
are as same as standard page program.
Thesequenceofissuing4PPinstructionis:CS#goeslow->sending4PPinstructioncode->3-byteaddressonSIO[3:0]-
> at least 1-byte on data on SIO[3:0]-> CS# goes high. (see Figure 20)
(15) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address after
each byte data has been programmed.
TheContinuouslyprogram(CP)instructionisformultiplebyteprogramtoFlash.AwriteEnable(WREN)instructionmust
executetosettheWriteEnableLatch(WEL)bitbeforesendingtheContinuouslyprogram(CP)instruction. CS#requires
togohighbeforeCPinstructionisexecuting. AfterCPinstructionandaddressinput,twobytesofdataisinputsequentially
from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 (or A0=1) and
secondbytedatawithA0=1(orA0=0). Ifonlyonebytedataisinput, theCPmodewillnotprocess. Ifmorethantwobytes
dataareinput,theadditionaldatawillbeignoredandonlytwobytedataarevalid.TheCPprograminstructionwillbeignored
and not affect the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase
state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will
exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status
ifitisnotinwriteprogressbeforeenteringnextvalidinstruction. DuringCPmode, thevalidcommandsareCPcommand
(ADhex),WRDIcommand(04hex),RDSRcommand(05hex),andRDSCURcommand(2Bhex).AndtheWRDIcommand
is valid after completion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low -> sending CP instruction code -> 3-byte address on SI pin
->twodatabytesonSI->CS#goeshightolow->sendingCPinstructionandthencontinue twodatabytesareprogrammed
->CS#goeshightolow->tilllastdesiredtwodatabytesareprogrammed->CS#goeshightolow->sendingWRDI(Write
Disable)instruction toendCPmode->sendRDSRinstructiontoverifyifCPmodewordprogramends,orsendRDSCUR
to check bit4 to verify if CP mode ends. (see Figure21 of CP mode timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program
cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP
mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage,
SOpinoutputstri-stateifCS#goeshigh. DSRY(disableSOtooutputRY/BY#)instructiontodisabletheSOtooutput
RY/BY#andreturntostatusregisterdataoutputduringCPmode.PleasenotethattheESRY/DSRYcommandarenot
accepted unless the completion of CP mode.
(16)DeepPower-down(DP)
TheDeepPower-down(DP)instructionisforsettingthedeviceontheminimizingthepowerconsumption(toenteringthe
DeepPower-downmode), thestandbycurrentisreducedfromISB1toISB2). TheDeepPower-downmoderequiresthe
P/N:PM1374
REV. 1.5, OCT. 01, 2008
21
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