MX25L1635D
(9) 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register
mustbesetto"1"beforesedingthe4READinstruction.TheaddressislatchedonrisingedgeofSCLK, anddataofevery
four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address can
be at any location. The address is automatically increased to the next higher address after each byte data is shifted out,
sothewholememorycanbereadoutatasingle4READinstruction.Theaddresscounterrollsoverto0whenthehighest
addresshasbeenreached. Oncewriting4READinstruction, thefollowingaddress/dummy/dataoutwillperformas4-bit
instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→sending 4READ instruction→24-bit address interleave
on SIO3, SIO2, SIO1 & SIO0→6 dummy cycles →data out interleave on SIO3, SIO2, SIO1 & SIO0→to end 4READ
operation can use CS# to high at any time during data out (see Figure 17 for 4 x I/O Read Mode Timing Waveform).
Anothersequenceofissuing4READinstructionespeciallyusefulinrandomaccessis:CS#goeslow→sending4READ
instruction→24-bitaddressinterleaveonSIO3, SIO2, SIO1&SIO0→performanceenhancetogglingbitP[7:0]→4dummy
cycles→dataoutinterleaveonSIO3,SIO2,SIO1andSIO0tillCS#goeshigh→CS#goeslow(reduce4Readinstruction)
→24-bit random access address (see figure 18 for 4x I/O read enhance performance mode timing waveform).
Intheperformance-enhancingmode(NoteofFigure.18),P[7:4]mustbetogglingwithP[3:0];likewiseP[7:0]=A5h,5Ah,F0h
or0Fhcanmakethismodecontinueandreducethenext4READinstruction.OnceP[7:4]isnolongertogglingwithP[3:0];
likewiseP[7:0]=FFh,00h,AAhor55h. AndafterwardsCS#israisedorissuingFFcommand(CS#goeshigh->CS#goes
low->sending0xFF->CS#goeshigh)insteadofnotoggling,thesystemthenwillescapefromperformanceenhancemode
and return to normal opertaion.In these cases,tSHSL=15ns(min) will be specified.
WhileProgram/Erase/WriteStatusRegistercycleisinprogress,4READinstructionisrejectedwithoutanyimpactonthe
Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any
4K-bytesector. AWriteEnable(WREN)instructionmustexecutetosettheWriteEnableLatch(WEL)bitbeforesending
the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The
CS# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the
instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#
goes high. (see Figure 22)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and
sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(11)BlockErase(BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-
byteblockeraseoperation.AWriteEnable(WREN)instructionmustexecutetosettheWriteEnableLatch(WEL)bitbefore
P/N:PM1374
REV. 1.5, OCT. 01, 2008
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