2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
REFIN
AGND
REFOUT
BANDGAP REFERENCE
10k
CH1A
CH1B
A
B
MUX
MUX
MUX
MUX
T/H
T/H
2.50V
CH2A
CH2B
A
B
V
REF
MUX
COMP
CH3A
A
B
T/H
T/H
CH3B
CH4A
12-BIT
DAC
A
B
SAR
CH4B
V
REF
A0
4x12
RAM
A1
D0/A2
D1/A3
D2
AV
DD
AGND
THREE-STATE
OUTPUT
DRIVERS
AV
SS
D3
D11 (MSB)
CONTROL LOGIC
10MHz
CLOCK
MAX115
MAX116
BUS INTERFACE
CLK
CONVST
INT
CS
RD
WR
DV
DGND
DD
Figure 2. Functional Diagram
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