2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
MAX115/MAX116
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= +5V ±5%, AV
SS
= -5V ±5%, DV
DD
= +5V ±5%, V
REFIN
= +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, f
CLK
= 16MHz, external clock, 50% duty cycle. T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Output High Voltage
Output Low Voltage
Three-State Leakage Current
Three-State Output
Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Digital Supply Voltage
Positive Supply Current
Negative Supply Current
Digital Supply Current
Shutdown Positive Current
Shutdown Negative Current
Shutdown Digital Current
Positive Supply Rejection
Negative Supply Rejection
Power Dissipation
PSRR+
PSRR-
(Note 10)
(Note 10)
(Note 11)
175
AV
DD
AV
SS
DV
DD
I
AVDD
I
AVSS
-20
4.75
-5.25
4.75
5
-5
5
17
-15
3
1
-1
13
±1
±1
6
5.25
-4.75
5.25
25
V
V
V
mA
mA
mA
µA
µA
µA
LSB
LSB
mW
SYMBOL
V
OH
V
OL
I
OUT
= 1mA
I
OUT
= -1.6mA
D0–D11
10
CONDITIONS
MIN
4
0.4
±10
TYP
MAX
UNITS
V
V
µA
pF
DIGITAL OUTPUTS
(D0–D11,
INT)
TIMING CHARACTERISTICS
(See Figure 4, AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, Typical values are at T
A
= +25°C,
unless otherwise noted.)
PARAMETER
CONVST
Pulse Width
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Low Pulse Width
Address Setup Time
Address Hold Time
RD
to
INT
Delay
Delay Time Between Reads
CS
to
RD
Setup Time
CS
to
RD
Hold Time
RD
Low Pulse Width
Data-Access Time
Bus-Relinquish Time
SYMBOL
t
CW
t
CWS
t
CWH
t
WR
t
AS
t
AH
t
ID
t
RD
t
CRS
t
CRH
t
RD
t
DA
t
DH
25pF load (Note 12)
25pF load (Note 13)
5
Guaranteed by design
Guaranteed by design
25pF load
45
0
0
30
40
45
Guaranteed by design
Guaranteed by design
CONDITIONS
MIN
30
0
0
30
30
0
55
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
