MV78100
Hardware Specifications
Table 22: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
DEV_WEn[1]
VDDO_C
DEV_WEn and DEV_OEn multiplexing option for A[16:15] bits
Defines if OE and WE are latched at first ALE cycle as A[15] and A[16].
This fact influences the OEn and WEn signal as follows:
0 = A[16:15] bits are not multiplexed on OE and WE signals.
NOTE: Whenever CS is inactive OE and WE are inactive.
1 = A[16:15] bits are multiplexed on OE and WE signals
NOTE: Whenever CS is inactive and ALE[1:0] are high, OE and WE are
inactive.
NOTE: Internally pulled down to 0x0.
DEV_WEn[2]
DEV_WEn[3]
DEV_A[0]
VDDO_C
VDDO_C
VDDO_C
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
TCLK Mode Select
0 = TCLK is driven from TCLK_IN input (De-skew mode)
1 = TCLK generated internally by TCLK PLL
NOTE: Internally pulled up to 0x1.
DEV_A[2:1]
VDDO_C
TCLK frequency select/TCLK De-skew PLL Tune
If DEV_A[0] is set to 1 - DEV_A[2:1] functions as TCLK frequency select:
0x0 = 166 MHz
0x1 = 200 MHz
0x2, 0x3 = Reserved
If DEV_A[0] is set to 0, DEV_A[2:1] functions as TCLK de-skew PLL Tune.
A setting recommendation will be released after chip silicon testing.
When using TCLK_IN input Board design should support future pull up/pull
down requirement on these pins. A final setting recommendation will be
published following silicon samples.
NOTE: Internally pulled to 0x1.
GE0_TXD[0]
VDD_GE
TCLK De-skewer PLL Frequency Band Select
Functions as TCLK De-Skewer PLL Frequency band select. Relevant for
De-skew mode only (DEV_A[0] is set to 0) .
0 = 166 MHz
1 = 200 MHz
NOTE: Internally pulled down to 0x0.
MV-S104552-U0 Rev. D
Page 56
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
