System Power Up and Reset Settings
Power Up and Boot Sequence
Table 22: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
GE0_TXD[1]
VDD_GE
Reserved
This signal must be sampled as 1 at reset de-assertion.
NOTE: Internally pulled up to 0x1.
GE0_TXD[3:2]
VDD_GE
DEV_ALE Mode Select
Defines DEV_ALE[1:0] behaviour in respect to address driven by device bus
controller (address setup and hold time in respect to DEV_ALE falling edge).
Useful for device bus topologies in which DEV_AD bus is heavily loaded.
0x0 = Address is driven for two TCLK cycles. ALE toggles after one TCLK
cycle.
0x1 = Address is driven for three TCLK cycles. ALE toggles after two TCLK
cycles.
0x2 = Address is driven for four TCLK cycles. ALE toggles after three TCLK
cycles.
0x3 = Reserved
NOTE: Internally pulled down to 0x0.
GE0_TXCTL
VDD_GE
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
Even if using a 8/16-bit device, the reset sampling on the upper device bus is still used.
Note
7.5
Power Up and Boot Sequence
The MV78100 requires that SYSRSTn remain asserted for at least 1 ms after power and clocks are
stable. The following procedure describes the boot sequence starting with the reset assertion:
1. While SYSRSTn is asserted, the PCLK, TCLK, and CLK125 PLLS are locked. SYSRSTn
assertion should be at least 1 ms.
2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK
cycles.
3. In parallel, TCLK de-skew PLL locks when working in de-skew mode.
4. If configured to boot from NAND Flash which does not support preload operation, the MV78100
also performs a NAND Flash boot init sequence.
Upon completing the above sequence, the CPU reset is deasserted, and CPU starts executing boot
code from DEV_BOOTCSn (whether it is a NOR Flash or a NAND Flash or from SPI Flash).
As part of the CPU boot code, the CPU typically performs the following:
Change the chip default address map if required, and configure PCI-Express address map.
Configure device bus timing parameters according to devices attached to device bus.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MV-S104552-U0 Rev. D
Document Classification: Proprietary Information
Page 57
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
