MV78100
Hardware Specifications
Configures the proper DRAM controller parameters, and then triggers DRAM initialization (set
DRAM Initialization Control register’s <InitEn> bit [0] to 1).
If using DRAM ECC, also initializes DRAM content. Initializes proper ECC to the entire DRAM
space.
Set the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.
MV-S104552-U0 Rev. D
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Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary