MV78100
Hardware Specifications
Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an
inactive state (LTSSM Detect state). When Link failure is detected:
A maskable interrupt is asserted
If the PCI Express Debug Control register’s <conf_dis_link_fail_reg_rst> is cleared, the
MV78100 also resets the PCI Express register file to its default values.
The MV78100 triggers an internal reset, if not masked by PCI Express Debug Control register’s
<conf_msk_link_fail> bit.
Whether initiated by a Hot Reset or link failure, this internal reset indication can be routed to
SYSRST_OUTn output as explained in Section 7.2, Hardware Reset, on page 51. The external
reset logic can assert SYSRSTn in response and reset the entire chip.
Only PEX0 port (or PEX0.0 port in Quad x1 configuration) can act as PCI Express
endpoint, and only this port can generate the PCI Express internal reset indication.
Note
7.4
Pins Sample Configuration
The following pins are sampled during SYSRSTn de-assertion. Internal pull up/down resistors set
the default mode. External pull up/down resistors are required to change the default mode of
operation. These signals must remain pulled up or down until SYSRSTn de-assertion (zero Hold
time in respect to SYSRSTn de-assertion).
If external logic is used instead of pull up and pull down resistors, the logic must drive
all of the signals to the desired values during SYSRSTn assertion. To prevent bus
contention on these pins, the external logic must float the bus no later than the third
TCLK cycle after SYSRSTn de-assertion. Refer to the MV76100, MV78100, and
MV78200 Design Guide for additional information.
Note
All reset sampled values are registered in Reset Sample (Low) and Reset Sample
(High) registers (see the Device Interface Registers in the MV76100, MV78100, and
MV78200 Functional Specification). This is useful for board debug purposes.
Multiple functionality applies to DEV_AD[31:9] and DEV_WEn[3:1], as described in
Section 6, Pin Multiplexing, on page 44. If an external device is driving any of these
signals, make sure to keep this external device in reset state (prevent it from driving) or
use glue logic to disconnect it from the MV78100 as long as the MV78100 SYSRSTn
input is asserted.
Table 22: Reset Configuration
Pin
Power Rail
Configuration Function
DEV_AD[0]
VDDO_C
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTES:
•
•
Internally pulled down to 0x0.
The board design should support future pull up/pull down requirements on
this pin.
Setting recommendations will be published following silicon samples.
MV-S104552-U0 Rev. D
Page 52
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
