MV78100
Hardware Specifications
Table 22: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
DEV_AD[13:12]
VDDO_C
PCLK to CPU L2 ratio
0x0 = 1
0x1 = 2
0x2 = 3
0x3 = Reserved
NOTE: Internally pulled to 0x1.
DEV_AD[17:14]
DEV_AD[19:18]
DEV_AD[20]
[15:14] VDDO_C
[17:16] VDDO_B
Reserved
NOTE: Internally pulled to 0x4.
Reserved
VDDO_B
VDDO_B
NOTE: Internally pulled to 0x1.
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
DEV_AD[22:21]
DEV_AD[24:23]
VDDO_B
VDDO_B
DEV_BootCEn Device Width
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
NOTE: Internally pulled down to 0x0.
Boot DeviceType Selection
0x0 = Boot from device bus
0x1 = Boot from SPI
0x2 = Boot from CE don’t care NAND Flash
0x3 = Boot from CE care NAND Flash
If DEV_AD[24:23] is set to 0x3, MPP[19:18] pins wake up as NAND Flash
outputs.
NOTE: Internally pulled down to 0x0.
DEV_AD[26:25]
VDDO_B
NAND Flash Initialization Sequence
Selects if NAND Flash initialization sequence is performed. Required for NAND
Flash devices that do not support preload feature. Only relevant if DEV_AD[24]
is set to 1 (boot from NAND Flash).
0x0 = No initialization
0x1 = Init sequence enabled, 3 address cycles
0x2 = Init sequence enabled, 4 address cycles
0x3 = Init sequence enabled, 5 address cycles
NOTE: Internally pulled down to 0x0.
DEV_AD[27]
VDDO_B
Big Endian/Little Endian mode
0 = Little Endian
1 = Big Endian
NOTE: Internally pulled down to 0x0.
MV-S104552-U0 Rev. D
Page 54
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
