System Power Up and Reset Settings
Pins Sample Configuration
Table 22: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
DEV_AD[1]
VDDO_C
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTES:
•
•
Internally pulled down to 0x0.
The board design should support future pull up/pull down requirements on
this pin.
Setting recommendations will be published following silicon samples.
DEV_AD[2]
VDDO_C
PCI Express Port0 mode select
0 = Endpoint
1 = Root Complex
NOTES:
•
•
Internally pulled up to 0x1.
When PCI Express port0 is configured to Quad x 1 (DEV_AD[3]=1), this bit
controls Port 0.0 only.
DEV_AD[3]
DEV_AD[4]
DEV_AD[7:5]
VDDO_C
VDDO_C
VDDO_C
PCI Express Port0 configuration
0 = x4
1 = Quad x1
NOTE: Internally pulled down to 0x0.
PCI Express Port1 configuration
0 = x4
1 = Quad x1
NOTE: Internally pulled up to 0x1.
HCLK Frequency select
0x0 = Reserved
0x1 = 200 MHz
0x2 = 267 MHz
0x3 = 333 MHz
0x4 = 400 MHz
0x5 = 250 MHz
0x6 = 300 MHz
0x7 = Reserved
NOTE: Internally pulled to 0x2.
DEV_AD[11:8]
VDDO_C
PCLK to HCLK ratio
0x0 = 1
0x1 = 1.5
0x2 = 2
0x3 = 2.5
0x4 = 3
0x5 = 3.5
0x6 = 4
0x7 = 4.5
0x8 = 5
0xB–0xF = Reserved
NOTE: Internally pulled to 0x4.
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 53
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
