System Power Up and Reset Settings
Hardware Reset
7.2
Hardware Reset
The MV78100 has one reset input pin — SYSRSTn. When asserted, the entire chip is placed in its
initial state. All outputs are placed in high-z.
The following output pins are still active during SYSRSTn assertion:
TCLK_OUT
GE0_TXCLKOUT
M_CLKOUT[2:0], M_CLKOUTn[2:0]
M_CKE[3:0]
M_ODT[3:0]
M_STARTBURST
SATAx_TX_P
SATAx_TX_N
PEXx_TX_N
PEXx_TX_P
USBx_DM
USBx_DP
The MV78100 has an optional SYSRST_OUTn open drain output signal, multiplexed on MPP pins,
that is used as a reset request from the MV78100 to the board reset logic. This signal is set when
one of the following maskable events occurs:
Received hot reset indication from the PCI Express port 0.0 link (only relevant when used as a
PCI Express endpoint), and bit <PexRstOutEn> is set to 1 in the RSTOUTn Mask Register (see
the Reset register section of the MV78100 User Manual). In this case, SYSRST_OUTn is
asserted for duration of ~300 TCLK cycles.
PCI Express port 0.0 link failure (only relevant when used as a PCI Express endpoint), and bit
<PexRstOutEn> is set to 1 in the RSTOUTn Mask Register (see the Reset register section of
the MV78100 User Manual). In this case, SYSRST_OUTn is asserted for duration of ~300
TCLK cycles .
Watchdog timer expiration and bit <WDRstOutEn> is set to 1 in the RSTOUTn Mask Register
(see the Reset register section of the MV78100 User Manual).
Bit <SystemSoftRst> is set to 1 in System Soft Reset Register and bit <SoftRstOutEn> is set to
1 in RSTOUTn Mask Register.
Reset must be active for a minimum length of 100ms. Core power, I/O power, and
analog power must be stable (VDD +/- 5%) during that time and onward.
Note
7.3
PCI Express Reset
As a Root Complex, the MV78100 can generate a Hot Reset to the PCI Express port. Upon CPU
setting the PCI Express Control register’s <conf_mstr_hot_reset> bit, the PCI Express unit sends a
Hot Reset indication to the Endpoint (see the PCI Express Interface section in the MV76100,
MV78100, and MV78200 Functional Specification).
When the MV78100 works as an Endpoint, and a Hot Reset packet is received:
A maskable interrupt is asserted
If the PCI Express Debug Control register’s <conf_dis_hot_rst_reg_rst> is cleared, the
MV78100 also resets the PCI Express register file to its default values.
The MV78100 triggers an internal reset, if not masked by PCI Express Debug Control register’s
<conf_msk_hot_reset> bit.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MV-S104552-U0 Rev. D
Document Classification: Proprietary Information
Page 51
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
