System Power Up and Reset Settings
Power Up/Down Sequence Requirements
7
System Power Up and Reset Settings
This section provides information about the MV78100 power-up sequence and configuration at
reset.
7.1
Power Up/Down Sequence Requirements
7.1.1
Power Up Sequence Requirements
These guidelines must be applied to meet the MV78100 device power-up requirements:
The Non-Core voltages (I/O and Analog) as listed in Table 21 must reach 70% of their voltage
level before the Core voltages reach 70% of their voltage level.
The order of the power up sequence between the Non-Core voltages is unimportant so long as
the Non-Core voltages power up before the Core voltages reach 70% of their voltage level
(shown in Figure 4).
The reset signal(s) must be asserted before the Core voltages reach 70% of their voltage level
(shown in Figure 4).
The reference clock(s) inputs must toggle with their respective voltage levels before the Core
Voltages reach 70% of their voltage level (shown in Figure 4).
Table 21: I/O and Core Voltages
Non-Core Voltages
Core Voltages
I/O Voltages
Analog Power Supplies
VDD_GE
VDD_M
PLL_AVDD
PEX0_AVDD
VDD
VDD_CPU
VDDO_A
VDDO_B
VDDO_C
VDDO_D
PEX1_AVDD
USB0_AVDD, USB1_AVDD, USB2_AVDD
SATA0_AVDD, SATA1_AVDD
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 49
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
