MV78100
Hardware Specifications
Table 20: MPP Function Summary (Continued)
MPP
Pin
0x0
0x1
0x2
0x3
0x4
0x5
0x6
DEV_
AD[10]
GPIO[18]
(in/out)
TDM_
RSTn
(out)
DEV_
AD[11]
GPIO[19]
(in/out)
TDM_
PCLK
(in/out)
DEV_
AD[12]
GPIO[20]
(in/out)
TDM_
FSYNC
(in/out)
DEV_
AD[13]
GPIO[21]
(in/out)
TDM_
DRX
(in)
DEV_
AD[14]
GPIO[22]
(in/out)
SATA0_ACT
n (out)
TDM_
DTX
(out)
DEV_
AD[15]
GPIO[23]
(in/out)
TDM1_
SCSn
(out)
DEV_
WEn[1]
GPIO[16]
(in/out)
DEV_
WEn[2]
GPIO[8]
(in/out)
SATA1_ACT
n (out)
DEV_
WEn[3]
GPIO[9]
(in/out)
SATA0_ACT
n (out)
M_BB (in)
Depending on the pin’s configured functionality, each pin can act as an output or input
pin. MPP[23:0] and DEV_AD[23:16] wake up as GPIO. All other pins wake up as
non-functional inputs pads (0x0 Column), with one exception. If the chip is configured at
reset to boot from CE Care NAND Flash, MPP[19:18] wake up as BOOT NAND Flash
output signals.
Note
The muxing options on DEV_AD[31:16] and DEV_WEn[3:2] only apply if all five device
chip selects are configured as 8- or 16-bit wide. Muxing options on DEV_AD[15:9] and
DEV_WEn[1] only apply if all five device chip selects are configured as 8-bit wide.
Where device bus pins multiplexing applies, these pins wake up as input (no drive).
MV-S104552-U0 Rev. D
Page 48
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
