Pin Multiplexing
MPP Multiplexing
Table 20: MPP Function Summary (Continued)
MPP
Pin
0x0
0x1
0x2
0x3
0x4
0x5
0x6
DEV_
AD[19]
GPIO[27]
(in/out)
UA2_RTSn
(out)
TDM_
FSYNC
(in/out)
DEV_
AD[20]
GPIO[28]
(in/out)
UA3_TXD
(out)
TDM_
DRX
(in)
DEV_
AD[21]
GPIO[29]
(in/out)
UA3_RXD
(in)
SYSRST_
OUTn (out)
TDM_
DTX
(out)
DEV_
AD[22]
GPIO[30]
(in/out)
UA3_CTSn
(in)
DEV_
AD[23]
GPIO[31]
(in/out)
UA3_RTSn
(out)
TDM1_
SCSn
(out)
DEV_
AD[24]
GPIO[0]
(in/out)
UA3_TXD
(out)
SYSRST_
OUTn (out)
TDM0_
RXQ
(out)
DEV_
AD[25]
GPIO[1]
(in/out)
UA3_RXD
(in)
TDM0_
TXQ
(out)
DEV_
AD[26]
GPIO[2]
(in/out)
UA2_TXD
(out)
TDM1_
RXQ
(out)
DEV_
AD[27]
GPIO[3]
(in/out)
UA2_RXD
(in)
TDM1_
TXQ
(out)
DEV_
AD[28]
GPIO[4]
(in/out)
UA0_CTSn
(in)
UA2_TXD
(out)
TDM0_
SCSn
(out)
DEV_
AD[29]
GPIO[5]
(in/out)
UA0_RTSn
(out)
UA2_RXD
(in)
SYSRST_
OUTn (out)
TDM_
SCLK
(out)
DEV_
AD[30]
GPIO[6]
(in/out)
UA1_CTSn
(in)
UA3_TXD
(out)
SYSRST_
OUTn (out)
TDM_
SMOSI
(out)
DEV_
AD[31]
GPIO[7]
(in/out)
UA1_RTSn
(out)
UA3_RXD
(in)
SYSRST_
OUTn (out)
TDM_
SMISO
(in)
DEV_
AD[9]
GPIO[17]
(in/out)
TDM_
INTn
(in)
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 47
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
