SXT6051 STM-1/0 SDH Overhead Terminator
In the case of a mismatch between the expected and
received J1 string, a J1MsMtch is indicated in register
A5H. In the case of a transmission error in the J1
string, a J1Crc7Err is indicated (16 byte case only) in
register A5H and will mask the J1MsMtch indication.
Pointer Recovery
Pointer Recovery Block
The pointer recovery block interprets the value of the
incoming pointer associated with either a VC-3 (STM-
0) or a VC-4 (STM-1) payload. The AU pointers
include two SS undefined bits. These bits can be either
ignored or recovered in the receive pointer processor
(see register 90H). The monitoring function of the
receive pointer processor includes the following
counters:
B3 Byte
This byte is used for Higher Order Path error monitor-
ing. The error events are counted in a 16 bit counter
accessible via registers 86H and 87H.
The B3 counter can be used either as a bit or a block
counter configurable via register 80H. Also, the
B3OUT output provides a pulse for each calculated B3
bit that is different from the received one.
• An 11-bit Positive Justification Counter accessi-
ble via register 91H and 92H
• An 11-bit Negative Justification Counter accessi-
ble via register 93H and 94H
C2 Byte
This block indicates the following conditions via reg-
ister A4H: an AU-AIS (all ones in the pointer), Loss of
Pointer (LOP) or New Data Flag (NDF).
This byte indicates the composition of the VC-3 or the
VC-4 payload. A change in the C2 byte for three or
five (configurable via register 80H) consecutive
frames is indicated in register A4H and allows the
updating of register 83H.
The LOP detection follows the ITU G 783 recommen-
dation using eight consecutive frames.
An “expected” value of C2 can be programmed in reg-
ister 82H. If the received C2 value is not equal to the
expected value and is not zero or one, this is indicated
in register A5H via the HptSlm (HPT Signal Label
Mismatch).
Receive Adaptation Section AIS (DmsaAIS)
The AIS generated after the Pointer recovery section is
labeled DmsaAis. It can be inserted on the following
conditions:
• AU-AIS detection (all ones pointer for three con-
secutive frames)
VC-AIS is defined as all ones in C2 (new G783 spec-
ifications). Five consecutive frames are required for
the VC-AIS detection which is indicated in register
A4H.
• LOP detection
The AIS can be disabled or forced via register 90H.
DmsaAis insertion is indicated in register D0H.
Unequipped Detection
To generate an “unequipped” indication, a set of four
simultaneous events need to be detected (see register
81H):
Higher Order Path Receiver
The Higher Order Path Receiver processes the over-
head bytes associated with the Higher Order Path
Overhead. All the Path Overhead bytes are accessible
at the RPOH output.
• C2 equal to all zero
• J1 equal to zero
• N1 equal to all zero
• No B3 errors
J1 Byte Path Trace
This byte is used to repetitively transmit a Path Access
Identifier so that a path receiver can verify its contin-
ued connection to the intended transmitter. The length
of the “expected” J1 string can be programmed to
either 64 bytes (non-specified) or 16 bytes with CRC7
(see register 80H). The 16 byte “expected” J1 string
value needs to have the correct CRC7 bits per G707
specifications. The receiver calculates the CRC7 of the
received J0 string.
The unequipped detector requires 5 frames before it is
indicated in register A5H.
G1 Byte
This byte conveys the path status and performance
back to a VC-3 or VC-4 trail termination source as
detected by a trail termination sink.
G1<7:4> bits act as a Remote Error Indication (REI).
They report the number of B3 errors detected at the
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LevelOne [ LEVEL ONE ]
