Functional Description
The Regenerator Section Trace J0
Receive Regenerator Section AIS (RstAIS)
The AIS generated after the Regenerator Section is
labeled RstAis. It can be inserted on the following con-
ditions:
This byte is used to repetitively transmit a Section
Access Identifier so that a section receiver can verify
its continued connection to the intended transmitter.
This byte has been defined in the latest specification of
ITU. To avoid compatibility problems with in-service
equipment, the chip can ignore J0 processing via reg-
ister 51H.
• Loss Of Signal (LOS)
• Loss Of Frame (LOF)
• Trace Identification Mismatch (J0MsMtch)
These conditions can be individually enabled or dis-
abled (see register 40H). A test register that can force
an RstAis for test purposes is also available. RstAis
insertion is indicated in register D0H.
The expected J0 string is configurable (see registers
0EH and 0FH). This J0 string value needs to have the
correct CRC7 bits per G707 specifications. The
receiver calculates the CRC7 of the received J0 string.
In the case of a mismatch between the expected &
received J0 string, a J0 mismatch (J0MsMtch) is indi-
cated in register A1H. In the case of a transmission
error in the J0 string, a J0 string CRC7 error
(J0Crc7Err) is indicated in register A1H and will mask
the J0MsMtch alarm.
National Used Bytes
The four RSOH “National Use” bytes are only acces-
sible in the STM-1 case. These bytes can be read via
registers 03H, 04H, 05H, and 06H or serially at the
RSOH output.
Media Dependent and Undefined Bytes
Bip-8 B1 Byte
The six “Media Dependent” and four “Undefined”
bytes are only accessible in the STM-1 case. These
bytes can only be read via the serial RSOH output.
This byte is used for Regenerator Section error moni-
toring. The error events are counted in a 16 bit counter
accessible via registers 45H and 46H.
Multiplexer Section Receiver
The Multiplexer Section receiver handles the MSOH
overhead bytes. All the overhead bytes (45 in STM-1
and 15 bytes in STM-0) are accessible at the RSOH
serial output.
The B1 counter can be configured as either a bit or a
block counter (see register 47H). Also, the B1OUT
output provides pulse for each calculated B1 bit that is
different from the one received.
E1 Orderwire Byte
This 64 Kbit/s channel is used to provide orderwire
channel for voice communication. The data is serially
accessible via RROW. The 64 KHz clock and the 8
KHz byte synchronization signals are used to receive
both the E2 and F1 bytes and are provided at pins
ROWC and ROWBYC.
B2 Error Byte
This byte is used for Multiplexer Section error moni-
toring. The B2 errors are counted either as block error
in register 10H and 11H (13 bit) or as bit errors in reg-
ister 12H, 13H and 14H (18-bit counter).
An Excessive Error Defect (EED) indication (see reg-
ister A1H) is generated by integrating the B2 errors in
a sliding window. Integration is also used when clear-
ing the EED indication. Six registers allow the config-
uration of EED indication thresholds. They are 18H,
15H, 16H, 17H, 1EH, 1BH, 1CH and 1DH.
F1 Byte
This 64 Kbit/s channel is reserved for the user’s pur-
pose. It can be used as an extra maintenance orderwire
access. The data is serially accessible via RDOW. The
64 KHz clock and the 8 KHz byte synchronization sig-
nals are used to receive both the E1 and E2 bytes and
are provided at pins ROWC and ROWBYC.
These six registers allow configuring the EED thresh-
old from a bit error rate of 10-3 to a bit error rate of 10-
9, even in the case of a non-Gaussian statistical distri-
bution of errors. An active EED indication can be con-
figured to insert an AIS signal (see register 20H).
D1 to D3 Data Channels
This 192 Kbit/s channel is used by the network man-
agement as a data channel. The data is accessible via
pin RRD and the clock is provided by RRDC. Note
that ROWBYC can be used as an 8KHz synchroniza-
tion if required.
30
l
LevelOne [ LEVEL ONE ]
