Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.)
LFE2-50
LFE2-70
Pin Type
Bank0
484 fpBGA
672 fpBGA
672 fpBGA
900 fpBGA
0
0
0
0
0
0
0
0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
2
3
3
4
0
3
3
3
Available DDR-Interfaces per I/O
Bank1
3
4
4
4
3
4
4
5
1
4
4
4
2
3
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI Capable I/Os per Bank
46
46
0
62
68
0
62
68
0
72
80
0
0
0
0
0
0
0
0
0
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
4-10
LATTICE [ LATTICE SEMICONDUCTOR ]
