Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35
LFE2-20
LFE2-35
208
PQFP
256
fpBGA
484
fpBGA
672
fpBGA
484
fpBGA
672
fpBGA
Pin Type
Single Ended User I/O
Differential Pair User I/O
131
62
5
193
331
402
331
450
224
5
96
165
200
165
TAP Pins
5
5
5
5
Configuration
Muxed Pins
14
7
14
14
14
14
14
7
Dedicated Pins (Non TAP)
Muxed Pins
7
7
7
7
42
3
54
60
64
60
68
3
Non Configuration
Dedicated Pins
3
3
3
3
VCC
14
8
7
18
24
16
22
16
2
VCCAUX
VCCPLL
4
16
16
16
0
0
0
0
2
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
2
2
4
5
4
5
2
2
4
5
4
5
2
2
4
5
4
5
2
2
4
5
5
4
5
VCCIO
2
2
4
4
5
2
2
4
5
4
5
2
2
2
4
4
5
4
4
5
2
5
5
2
1
2
2
2
2
GND, GND0 to GND7
NC
22
0
20
60
72
60
72
102
67/33
52/26
48/24
42/21
54/27
68/34
58/29
47/23
14/7
0
1
8
101
67/33
52/26
36/18
32/16
50/25
68/34
48/24
35/17
14/7
0
8
Bank0
18/9
18/9
11/5
11/5
19/9
18/9
18/8
12/6
6/2
0
18/9
34/17
20/10
12/6
32/16
17/8
26/13
20/10
14/7
0
50/25
46/23
34/17
22/11
46/23
46/23
40/20
33/16
14/7
0
50/25
46/23
34/17
22/11
46/23
46/23
40/20
33/16
14/7
0
Bank1
Bank2
Bank3
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
0
0
0
0
0
0
4
5
9
9
9
12
9
3
3
5
8
5
True LVDS I/O Pairs per Bank
0
0
0
0
0
0
0
0
0
0
0
0
6
7
10
12
10
13
11
0
5
5
8
8
8
0
0
0
0
0
4-7
LATTICE [ LATTICE SEMICONDUCTOR ]
