Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and
LFE2M100
LFE2M50
LFE2M70
LFE2M100
Pin Type
Single Ended User I/O
484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA
270
135
5
372
185
5
410
205
5
416
208
5
436
218
5
416
207
5
520
260
5
Differential Pair User I/O
TAP Pins
Muxed Pins
14
14
14
14
14
14
14
Configuration
Dedicated Pins
(Non TAP)
7
7
7
7
7
7
7
Muxed Pins
69
72
3
72
3
75
3
76
3
74
3
78
3
Non Configuration
Dedicated Pins
3
VCC
16
20
26
8
62
44
16
4
44
44
16
4
44
VCCAUX
VCCPLL
8
18
12
12
4
4
4
4
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
4
5
6
6
7
6
7
3
4
6
6
7
6
7
4
4
5
9
9
9
9
9
5
9
9
9
9
9
VCCIO
4
4
6
6
7
6
7
4
5
6
6
7
6
7
4
5
9
9
9
9
9
4
5
9
9
9
9
9
2
2
2
2
2
2
2
GND, GND0 to GND7
NC
57
80
35
63/31
18/9
50/25
43/21
24/12
60/30
54/27
60/30
0/0
0
122
121
56/28
36/18
54/27
44/22
38/19
58/29
60/30
64/32
0/0
0
122
63
34/17
42/21
70/35
60/30
38/19
40/20
62/31
70/35
0/0
0
134
283
46/23
34/17
72/36
64/32
40/20
40/20
66/33
74/37
0/0
0
122
63
34/17
42/21
70/35
60/30
38/19
40/20
62/31
70/35
0/0
0
134
199
54/27
44/22
80/40
80/40
44/22
46/23
82/41
90/45
0/0
0
31
Bank0
36/18
18/9
30/15
36/18
42/21
28/14
40/20
40/20
0/0
0
Bank1
Bank2
Bank3
Single Ended/ Differential
I/O Pairs per Bank (includ-
ing emulated with resis-
tors)
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
0
0
0
0
0
0
0
7
12
11
0
13
17
15
0
18
17
15
0
20
9
11
16
20
True LVDS I/O Pairs per
Bank
0
0
0
0
0
0
0
0
0
0
0
10
14
15
0
15
15
17
0
16
15
17
0
20
10
17
18
22
0
0
0
0
4-13
LATTICE [ LATTICE SEMICONDUCTOR ]
