Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35
LFE2M20
LFE2M35
Pin Type
256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA
Single Ended User I/O
Differential Pair User I/O
140
304
140
303
410
199
5
70
152
70
151
TAP Pins
5
5
5
5
Configuration
Muxed Pins
14
14
14
14
14
7
Dedicated Pins (Non TAP)
Muxed Pins
7
7
7
7
64
84
60
84
89
3
Non Configuration
Dedicated Pins
3
3
3
3
VCC
6
16
6
16
29
17
8
VCCAUX
VCCPLL
4
8
4
8
1
4
1
4
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
1
1
4
1
1
4
5
3
3
4
2
4
4
2
4
4
5
2
2
5
VCCIO
2
4
2
4
4
2
4
2
4
5
2
4
2
4
5
2
4
2
4
5
1
2
1
2
2
GND, GND0 to GND7
NC
22
17
0/0
0/0
14/7
16/8
32/16
20/10
16/8
28/14
14/7
0
57
22
17
0/0
0/0
14/7
16/8
32/16
20/10
16/8
28/14
14/7
0
57
80
37
63/31
18/9
50/25
43/21
50/21
60/30
52/25
60/30
14/7
0
11
12
Bank0
36/18
18/9
30/15
36/18
62/31
28/14
40/20
40/20
14/7
0
36/18
18/9
30/15
36/18
62/31
28/14
39/19
40/20
14/7
0
Bank1
Bank2
Bank3
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
0
0
0
0
0
3
7
3
7
12
11
0
4
9
4
9
True LVDS I/O Pairs per Bank Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
0
0
0
0
0
0
0
0
0
Bank6 (Left Edge)
4
10
4
10
14
15
0
Bank7 (Left Edge)
7
10
7
10
Bank8 (Right Edge)
0
0
0
0
4-11
LATTICE [ LATTICE SEMICONDUCTOR ]
