Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70
LFE2-50
LFE2-70
Pin Type
484 fpBGA
672 fpBGA
672 fpBGA
900 fpBGA
Single Ended User I/O
Differential Pair User I/O
339
500
249
5
500
249
5
583
290
5
169
TAP Pins
5
Configuration
Muxed Pins
14
14
7
14
7
14
Dedicated Pins (Non TAP)
Muxed Pins
7
7
68
79
3
79
3
89
Non Configuration
Dedicated Pins
3
3
VCC
16
20
16
4
20
16
2
26
VCCAUX
VCCPLL
16
17
4
4
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
4
5
5
6
4
5
5
6
4
5
5
6
4
5
5
6
VCCIO
4
5
5
6
4
5
5
6
4
4
5
5
6
5
5
6
2
2
2
2
GND, GND0 to GND7
NC
60
72
3
72
5
104
101
84/42
76/38
74/37
48/24
72/35
80/40
64/32
71/35
14/7
0
0
Bank0
50/25
46/23
38/19
22/11
46/23
46/23
40/20
37/18
14/7
0
67/33
66/33
56/28
48/24
62/31
68/34
64/32
55/27
14/7
0
67/33
66/33
56/28
48/24
62/31
68/34
64/32
55/27
14/7
0
Bank1
Bank2
Bank3
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
0
0
0
0
9
13
12
0
13
12
0
18
5
12
True LVDS I/O Pairs per Bank
0
0
0
0
0
0
10
16
12
0
16
12
0
16
8
16
0
0
4-9
LATTICE [ LATTICE SEMICONDUCTOR ]
