Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100
(Cont.)
LFE2M50
LFE2M70
LFE2M100
Pin Type
Bank0
484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
2
4
2
4
4
4
4
2
3
1
3
4
3
5
Available DDR-Interfaces
per I/O Bank1
3
1
3
3
3
3
3
2
3
3
2
3
2
3
1
3
2
3
4
3
5
3
4
3
4
4
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
72
64
40
40
66
74
0
0
80
80
44
46
82
90
0
0
0
0
0
0
PCI Capable I/Os per Bank Bank4
50
60
52
60
0
24
60
54
60
0
48
50
60
68
0
48
40
62
70
0
48
40
62
70
0
Bank5
Bank6
Bank7
Bank8
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
4-14
LATTICE [ LATTICE SEMICONDUCTOR ]
