Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.)
LFE2-6
LFE2-12
144
256
144
208
256
484
Pin Type
Bank0
TQFP
fpBGA
TQFP
PQFP
fpBGA
fpBGA
0
0
0
0
0
0
0
0
0
0
0
0
0
18
8
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
1
0
0
1
1
0
0
0
0
0
Available DDR-Interfaces per I/O
Bank1
2
0
0
2
3
1
0
0
1
3
1
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI Capable I/Os per Bank
32
14
0
18
10
0
19
18
0
32
17
0
46
46
0
0
0
0
0
0
0
0
0
0
0
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
4-6
LATTICE [ LATTICE SEMICONDUCTOR ]
