Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.)
LFE2M20
LFE2M35
Pin Type
Bank0
256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA
0
0
0
0
0
0
0
0
0
0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
0
1
0
1
3
0
1
0
1
2
Available DDR-Interfaces per
I/O Bank1
2
4
2
4
3
1
2
1
2
3
0
3
0
1
2
1
2
1
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI Capable I/Os per Bank
32
20
16
28
0
62
28
40
40
0
32
20
16
28
0
62
28
39
40
0
50
60
52
60
0
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
4-12
LATTICE [ LATTICE SEMICONDUCTOR ]
