Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12
LFE2-6
LFE2-12
144
256
144
208
256
484
Pin Type
TQFP
fpBGA
TQFP
PQFP
131
62
5
fpBGA
fpBGA
Single Ended User I/O
Differential Pair User I/O
90
43
5
190
93
45
5
193
297
95
96
148
TAP Pins
5
5
5
Configuration
Muxed Pins
14
7
14
14
7
14
7
14
14
Dedicated Pins (Non TAP)
Muxed Pins
7
7
7
34
3
54
33
3
40
3
54
57
Non Configuration
Dedicated Pins
3
3
3
VCC
10
4
7
10
4
14
8
7
16
VCCAUX
VCCPLL
4
4
16
0
0
0
0
0
0
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
1
2
1
2
2
4
1
2
1
2
2
4
1
2
1
2
2
4
1
2
1
2
2
4
VCCIO
1
2
1
2
2
4
1
2
1
2
2
4
4
1
2
2
1
2
2
2
1
1
2
4
1
1
1
2
1
2
GND, GND0 to GND7
NC
12
4
20
12
1
22
0
20
60
3
0
44
Bank0
8/4
17/8
4/2
8/4
18/9
8/4
9/4
12/6
6/2
0
18/6
34/17
20/10
12/6
32/16
14/7
26/13
20/10
14/7
0
8/4
18/9
4/2
8/4
18/9
10/5
9/4
12/6
6/2
0
18/9
18/9
11/5
11/5
19/9
18/9
18/8
12/6
6/2
0
18/9
34/17
20/10
12/6
32/16
17/8
26/13
20/10
14/7
0
50/25
46/23
24/12
16/8
46/23
46/23
32/16
23/11
14/7
0
Bank1
Bank2
Bank3
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
0
0
0
0
0
0
1
5
1
4
5
6
3
3
3
3
3
4
True LVDS I/O Pairs per Bank
0
0
0
0
0
0
0
0
0
0
0
0
2
7
2
6
7
8
5
5
5
5
5
5
0
0
0
0
0
0
4-5
LATTICE [ LATTICE SEMICONDUCTOR ]
