Specifications
ispLSI 3256A
Internal Timing Parameters
1
Over Recommended Operating Conditions
PARAMETER
Inputs
#
2
DESCRIPTION
-90
-70
-50
MIN. MAX. MIN. MAX. MIN. MAX.
–
–
5.7
-3.7
–
–
–
–
–
–
–
–
–
1.0
4.8
–
–
–
–
2.8
–
–
1.9
10.9
–
–
4.2
2.8
2.4
4.8
4.8
5.4
6.4
6.9
0.1
–
–
1.6
2.6
8.6
4.9
5.3
2.3
0.9
–
–
6.2
-5.2
–
–
–
–
–
–
–
–
–
1.8
6.0
–
–
–
–
3.2
–
–
2.4
12.4
–
–
4.2
3.6
3.0
5.9
5.9
6.4
7.4
8.1
0.1
–
–
1.8
2.8
10.5
5.4
6.3
2.7
1.2
–
–
8.6
–
–
–
–
–
–
–
–
–
-7.0
3.3
15.8
UNITS
26 I/O Register Setup Time before Clock
27 I/O Register Hold Time after Clock
28 I/O Register Clock to Out Delay
29 I/O Register Reset to Out Delay
30 GRP Delay
31 4 Product Term Bypass Path Delay (Comb.)
32 4 Product Term Bypass Path Delay (Reg.)
33 1 Product Term/XOR Path Delay
34 20 Product Term/XOR Path Delay
35 XOR Adjacent Path Delay
3
36 GLB Register Bypass Delay
37 GLB Register Setup Time before Clock
38 GLB Register Hold Time after Clock
39 GLB Register Clock to Output Delay
40 GLB Register Reset to Output Delay
41 GLB Product Term Reset to Register Delay
42 GLB Product Term Output Enable to I/O Cell Delay
43 GLB Product Term Clock Delay
44 ORP Delay
45 ORP Bypass Delay
FOR NEW D
ESIGNS
–
–
5.3
4.9
4.1
7.6
7.6
8.8
10.1
0.1
–
–
11.1
2.2
3.8
14.2
7.3
8.5
3.6
1.6
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
GRP
24 I/O Register Bypass
25 I/O Latch Delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
grp
GLB
ORP
t
orp
t
orpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
USE 3256A-
70
2.4
–
8.2
–
–
–
4.3
–
–
t
4ptbp
t
4ptbp
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
Table 2-0036C/3256A
LATTICE [ LATTICE SEMICONDUCTOR ]
