Specifications ispLSI 3256A
Internal Timing Parameters1
Over Recommended Operating Conditions
-90
-70
-50
2
PARAMETER
#
DESCRIPTION
UNITS
MIN. MAX.
MIN. MAX. MIN. MAX.
Inputs
tiobp
tiolat
tiosu
tioh
–
–
1.9
10.9
–
24 I/O Register Bypass
–
–
2.4
12.4
–
–
–
3.3
15.8
–
ns
ns
ns
ns
ns
ns
25 I/O Latch Delay
5.7
-3.7
–
26 I/O Register Setup Time before Clock
27 I/O Register Hold Time after Clock
28 I/O Register Clock to Out Delay
29 I/O Register Reset to Out Delay
6.2
-5.2
–
8.6
-7.0
–
–
–
–
4.2
2.8
4.2
3.6
5.3
4.9
tioco
tior
–
–
–
GRP
–
2.4
30 GRP Delay
–
3.0
–
4.1
ns
tgrp
GLB
–
–
4.8
4.8
5.4
6.4
6.9
0.1
–
31 4 Product Term Bypass Path Delay (Comb.)
32 4 Product Term Bypass Path Delay (Reg.)
33 1 Product Term/XOR Path Delay
–
–
5.9
5.9
6.4
7.4
8.1
0.1
–
–
–
7.6
7.6
8.8
10.1
11.1
0.1
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t4ptbp
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ORP
torp
–
–
–
–
34 20 Product Term/XOR Path Delay
35 XOR Adjacent Path Delay3
–
–
–
–
–
–
36 GLB Register Bypass Delay
–
–
1.0
4.8
–
37 GLB Register Setup Time before Clock
38 GLB Register Hold Time after Clock
39 GLB Register Clock to Output Delay
40 GLB Register Reset to Output Delay
41 GLB Product Term Reset to Register Delay
42 GLB Product Term Output Enable to I/O Cell Delay
43 GLB Product Term Clock Delay
1.8
6.0
–
2.4
8.2
–
–
–
–
1.6
2.6
8.6
4.9
1.8
2.8
10.5
5.4
2.2
3.8
14.2
7.3
–
–
–
–
–
–
–
–
–
2.8 5.3
3.2 6.3
4.3 8.5
–
–
2.3
0.9
44 ORP Delay
–
–
2.7
1.2
–
–
3.6
1.6
ns
ns
45 ORP Bypass Delay
torpbp
Table 2-0036C/3256A
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
LATTICE [ LATTICE SEMICONDUCTOR ]
