Specifications
ispLSI 3256A
Internal Timing Parameters
1
Over Recommended Operating Conditions
PARAMETER
Outputs
#
2
DESCRIPTION
-90
-70
-50
MIN. MAX. MIN. MAX. MIN. MAX.
–
–
–
–
2.7
0.7
–
–
–
1.9
11.9
6.8
6.8
2.7
3.7
6.7
2.3
3.2
–
–
–
–
3.6
1.2
–
–
–
UNITS
t
ob
t
obs
t
oen
t
odis
Clocks
46 Output Buffer Delay
47 Output Buffer Delay, Slew Limited Adder
48 I/O Cell OE to Output Enabled
49 I/O Cell OE to Output Disabled
50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line
51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
52 Global Reset to GLB and I/O Registers
53 Global OE Pad Buffer
54 Test OE Pad Buffer
USE 3256A-
70 FOR
NEW DESIG
NS
–
3.3
–
13.3
9.8
9.8
–
–
4.9
4.9
1.6
–
7.0
9.6
–
3.7
–
13.2
2.4
12.4
7.2
7.2
3.6
5.2
7.1
2.8
9.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
gy0/1/2
t
ioy3/4
Global Reset
t
gr
t
goe
t
toe
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Table 2-0037C/3256A
8
LATTICE [ LATTICE SEMICONDUCTOR ]
