Specifications ispLSI 3256A
Description (continued)
All local logic block outputs are brought back into the An additional feature of the ispLSI 3256A is its Boundary
GRP so they can be connected to the inputs of any other Scan capability, which is composed of cells connected
logic block on the device. The device also has 128 I/O between the on-chip system logic and the device’s input
cells, each of which is directly connected to an I/O pin. and output pins. All I/O pins have associated boundary
Each I/O cell can be individually programmed to be a scan registers, with 3-state I/O using three boundary
combinatorialinput,aregisteredinput,alatchedinput,an scan registers and inputs using one.
output or a bidirectional I/O pin with 3-state control. The
The ispLSI 3256A supports the full boundary scan IEEE
signal levels are TTL compatible voltages and the output
1149.1 specification for ISP programming and board-
drivers can source 4 mA or sink 8 mA. Each output can
level tests via the TAP controller port. It is also fully
be programmed independently for fast or slow output
backward compatible to the Lattice ISP interface. While
slew rate to minimize overall output switching noise.
fully JEDEC file and functionally compatible with the
The 128 I/O cells are grouped into eight sets of 16 bits. earlier ispLSI 3256 devices, the 3256A requires a modi-
Each of these I/O groups is associated with a logic fied Boundary Scan Description Library (BSDL) model to
Megablock through the use of the ORP. These groups of support boundary scan test and programming. As a
16I/OcellsshareoneProductTermOutputEnablewhich result, existing 3256 test programs that use the boundary
is associated with a specific pair of Megablocks and two scan test feature must be updated to use the 3256A.
Global Output Enables.
Please contact Lattice Applications for the new model.
Four Twin GLBs, 16 I/O cells and one ORP are con- The ispLSI 3256A supports all IEEE 1149.1 mandatory
nected together to make a logic Megablock. The instructions, which include BYPASS, EXTEST and
Megablockisdefinedbythe resourcesthatitshares. The SAMPLE.
outputs of the four Twin GLBs are connected to a set of
16 I/O cells by the ORP. The ispLSI 3256A device
contains eight of these Megablocks.
Key Attributes of the ispLSI 3256A
Attribute
Twin GLBs
Quantity
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
32
384
128
5
Registers
I/O Pins
Global Clocks
Global OE
Test OE
Clocks in the ispLSI 3256A device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
2
1
Table 1-0003A/3256
The table at right lists key attributes of the device along
with the number of resources available.
3
LATTICE [ LATTICE SEMICONDUCTOR ]
