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IC42S16100E-6TL 参数 Datasheet PDF下载

IC42S16100E-6TL图片预览
型号: IC42S16100E-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 81 页 / 1082 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS42S16100E, IC42S16100E  
Bank Active Command Interval  
thatbankwithintheACTtoPREcommandperiod(tr a s max).  
Also note that a precharge command cannot be executed  
for an active bank before tr a s (min) has elapsed.  
When the selected bank is precharged, the period trp  
has elapsed and the bank has entered the idle state,  
the bank can be activated by executing the active  
command. If the other bank is in the idle state at that  
time, the active command can be executed for that bank  
after the period tr r d has elapsed. At that point both  
banks will be in the active state. When a bank active  
command has been executed, a precharge command  
must be executed for  
After a bank active command has been executed and  
the trcd period has elapsed, read write (including auto-  
precharge) commands can be executed for that bank.  
CLK  
tRRD  
COMMAND  
ACT 0  
ACT 1  
BANK ACTIVE (BANK 0)  
BANK ACTIVE (BANK 1)  
CLK  
COMMAND  
tRCD  
ACT 0  
READ 0  
BANK ACTIVE (BANK 0)  
BANK ACTIVE (BANK 0)  
CAS latency = 3  
Clock Suspend  
When the CKE pin is dropped from HIGH to LOW during  
a read or write cycle, the IS42S16100E/IC42S16100E  
enters clock suspend mode on the next CLK rising edge.  
This command reduces the device power dissipation by  
stopping the device internal clock. Clock suspend mode  
continues as long as the CKE pin remains low. In this  
state, all inputs other than CKE pin are invalid and no  
othercommandscanbeexecuted.Also,thedeviceinternal  
states are maintained. When the CKE pin goes from LOW  
to HIGH clock suspend mode is terminated on the next  
CLK rising edge and device operation resumes.  
The next command cannot be executed until the recovery  
period (tc k a ) has elapsed.  
Sincethiscommanddiffersfromtheself-refreshcommand  
described previously in that the refresh operation is not  
performed automatically internally, the refresh operation  
must be performed within the refresh period (tref). Thus  
the maximum time that clock suspend mode can be held  
is just under the refresh cycle time.  
CLK  
CKE  
COMMAND  
DQ  
READ 0  
D
OUT  
0
DOUT  
1
DOUT  
2
DOUT 3  
READ (BANK 0)  
CLOCK SUSPEND  
CAS latency = 2, burstlength = 4  
36  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. C  
01/22/08  
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