AS7C33512NTD16A
AS7C33512NTD18A
®
Synchronous truth table
CE0
H
X
CE1
X
CE2
X
ADV/LD
R/W BW[a,b] OE
CEN Address source
CLK
Operation
L
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
L
L
NA
NA
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Begin read
L
X
X
X
H
L
L
X
L
NA
L
H
H
X
L
X
L
External
External
Burst counter
Stall
L
L
L
L
L
L to H Begin write
L to H Burst2
X
X
H
X
X
X
X1
L
X
X
X
X
H
L to H Inhibit the CLK
1 Should be low for Burst write, unless a specific byte/s need/s to be inhibited
2 Refer to state diagram below.
Key: X = Don’t Care, L = Low, H = High.
State Diagram for NTD SRAM
Burst
Read
Burst
Read
Read
Burst
Read
Dsel
Dsel
Burst
Burst
Burst
Write
Write
Burst
Write
Write
Recommended operating conditions
Parameter
Symbol
VDD
VSS
Min
3.135
0.0
Nominal
Max
3.6
Unit
3.3
0.0
3.3
0.0
2.5
0.0
–
Supply voltage
V
0.0
VDDQ
VSSQ
VDDQ
VSSQ
VIH
3.135
0.0
3.6
3.3V I/O supply
voltage
V
V
V
0.0
2.35
0.0
2.65
0.0
2.5V I/O supply
voltage
2.0
–0.52
VDD + 0.3
0.8
Address and
control pins
VIL
–
Input voltages1
VIH
2.0
–
VDDQ + 0.3
0.8
I/O pins
V
VIL
–0.52
0
–
Ambient operating temperature
TA
–
70
°C
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 × t
.
IL
RC
3/11/02; v.1.8H
Alliance Semiconductor
5 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
