AS7C33512NTD16A
AS7C33512NTD18A
®
Timing characteristics over operating range
-166 H
–166
–150
–133
–100
Parameter
Symbol
fMax
tCYC
tCYCF
tCD 3.3V
tCD 2.5V
tCDF
Unit Notes1
Min Max Min Max Min Max Min Max Min Max
Clock frequency
–
6
166
–
–
6
166
–
–
150
–
–
133
–
–
100 MHz
Cycle time (pipelined mode)
6.6
10
–
7.5
12
–
10
12
–
–
–
ns
ns
Cycle time (flow-through mode)
Clock access time (pipelined mode)- 3.3V V
Clock access time (pipelined mode)- 2.5V V
Clock access time (flow-through mode)
Output enable LOW to data valid
Clock HIGH to output Low Z
10
–
–
10
–
–
–
–
3.0
4.0
9
3.5
4.0
9
3.8
4.3
10
3.8
–
4.0
4.5
10
4.0
–
5.0 ns
5.0 ns
12 ns
5.0 ns
DDQ
DDQ
–
–
–
–
–
–
–
–
–
–
tOE
–
3.5
–
–
3.5
–
–
–
–
tLZC
0
0
0
0
0
–
–
–
ns
ns
ns
2,3,4
2
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
Clock HIGH pulse width
tOH
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
tLZOE
tHZOE
tHZC
tOHOE
tCH
–
–
–
–
2,3,4
2,3,4
2,3,4
–
3.0
3.0
–
–
3.5
3.5
–
–
3.8
3.8
–
–
4.0
4.0
–
–
4.5 ns
5.0 ns
–
–
–
–
–
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
2.4
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
–
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
3.5
3.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
5
5
Clock LOW pulse width
tCL
–
–
–
–
Address setup to clock HIGH
tAS
–
–
–
–
6
Data setup to clock HIGH
tDS
–
–
–
–
6
Write setup to clock HIGH
tWS
–
–
–
–
6,7
6,8
6
Chip select setup to clock HIGH
ADV/LD setup to clock HIGH
tCSS
–
–
–
–
tADVS
tCENS
tAH
–
–
–
–
Clock enable
ꢀ
setup to clock HIGH
–
–
–
–
6
Address hold from clock HIGH
Data hold from clock HIGH
–
–
–
–
6
tDH
–
–
–
–
6
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV/LD hold from clock HIGH
tWH
–
–
–
–
6,7
6,8
6
tCSH
–
–
–
–
tADVH 0.5
tCENH 0.5
–
–
–
–
Clock enable hold from clock HIGH
–
–
–
–
6
1 Refer to “notes” on page 10.
3/11/02; v.1.8H
Alliance Semiconductor
7 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
