AS7C33512NTD16A
AS7C33512NTD18A
®
Functional description
The AS7C33512NTD16A/18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 16 or 18 bits and incorporates a LATE LATE Write.
™
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced write operation that
improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the
device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
™
NTD devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough)
™
read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD , write and
read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16/18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD16A and AS7C33512NTD18A operate with a 3.3V 5ꢀ power supply for the device core (V ). DQ circuits use a sepa-
DD
rate power supply (V
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP and a 119-ball
DDQ
14×20 mm BGA package.
Capacitance
Parameter
Symbol
CIN
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
Max
5
Unit
pF
Input capacitance
I/O capacitance
CI/O
VIN = VOUT = 0V
7
pF
Burst Order
Interleaved Burst Order
LBO=1
Linear Burst Order
LBO=0
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
10
11
00
01
11
10
01
00
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
10
11
00
10
11
00
01
11
00
01
10
00
11
10
3/11/02; v.1.8H
Alliance Semiconductor
3 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
