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AS7C33512NTD18A-100BI 参数 Datasheet PDF下载

AS7C33512NTD18A-100BI图片预览
型号: AS7C33512NTD18A-100BI
PDF下载: 下载PDF文件 查看货源
内容描述: [ZBT SRAM, 512KX18, 12ns, CMOS, PBGA119, 14 X 20 MM, BGA-119]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 12 页 / 299 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C33512NTD16A  
AS7C33512NTD18A  
®
Signal descriptions  
Signal  
CLK  
I/O Properties  
Description  
I
CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.  
CEN  
I
I
SYNC  
SYNC  
SYNC  
Clock enable. When de-asserted HIGH, the clock input signal is masked.  
Address. Sampled when all chip enables are active and ADV/LD is asserted.  
Data. Driven as output when the chip is enabled and OE is active.  
A, A0, A1  
DQ[a,b]  
I/O  
CE0, CE1,  
CE2  
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are  
ignored when ADV/LD is HIGH.  
I
I
I
SYNC  
Advance or Load. When sampled HIGH, the internal burst address counter will increment in  
the order defined by the LBO input value. (refer to table on page 2) When LOW, a new  
address is loaded.  
ADV/LD  
R/W  
SYNC  
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE  
operation. Is ignored when ADV/LD is HIGH.  
SYNC  
SYNC  
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE  
command and BURST WRITE.  
BW[a,b]  
OE  
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.  
Count mode. When driven High, count sequence follows Intel XOR convention. When  
STATIC driven Low, count sequence follows linear convention. This input should be static when the  
device is in operation.  
LBO  
I
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD  
if unused or for pipelined operation.  
FT  
I
STATIC  
ZZ  
I
ASYNC Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.  
NC  
-
-
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.  
Absolute maximum ratings  
Parameter  
Symbol  
VDD, VDDQ  
VIN  
Min  
–0.5  
–0.5  
–0.5  
Max  
+4.6  
Unit  
V
Power supply voltage relative to GND  
Input voltage relative to GND (input pins)  
Input voltage relative to GND (I/O pins)  
Power dissipation  
VDD + 0.5  
VDDQ + 0.5  
1.8  
V
VIN  
V
PD  
W
mA  
°C  
°C  
DC output current  
IOUT  
50  
Storage temperature (plastic)  
Temperature under bias  
Tstg  
–65  
–65  
+150  
Tbias  
+135  
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-  
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions may affect reliability.  
3/11/02; v.1.8H  
Alliance Semiconductor  
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