AS7C331MPFS18A
®
Synchronous truth table
1
CE0
H
L
CE1
X
L
CE2 ADSP ADSC ADV BWn
OE Address accessed
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z2
Hi−Z
Hi−Z2
Hi−Z
Q
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
F
X
X
X
X
X
L
NA
NA
Lto H
Lto H
Lto H
Lto H
Lto H
L to H
L to H
Lto H
Lto H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Lto H
L to H
L to H
L to H
L to H
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
F
H
L
Begin read
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
F
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
F
H
L
Next
Hi−Z
Q
H
H
L
F
Current
Current
Next
F
H
L
Hi−Z
Q
F
L
F
H
L
Next
Hi−Z
Q
H
H
X
L
F
Current
Current
External
Next
F
H
X
X
X
X
X
Hi−Z
D3
T
T
T
T
T
X
H
X
H
X
X
X
X
H
H
H
H
D
L
Next
D
H
H
Current
Current
D
D
1 See “Write enable truth table” on page 4 for more information.
2 Q in flow-through mode.
3 For a write operation following a read operation, OE must be high before the input data set up time and must be held high throughout the input hold time
Key: X = don’t care, L = low, H = high
TQFP and BGA thermal resistance
Description
Symbol
Typical
40
Units Conditions
1 layer
4 layer
θ
°C/ W
Thermal resistance
JA
Test conditions follow standard test
(junction to ambient)1
θ
22
°C/ W
methods and procedures for
measuring thermal impedance, per
EIA/ JESD51
JA
JC
Thermal resistance
θ
8
°C/ W
(junction to top of case)1
1 This parameter is sampled.
12/ 2/ 02, v. 0.9.2 Advance Info
Alliance Semiconductor
5 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
