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AS7C331MPFS18A-250TQC 参数 Datasheet PDF下载

AS7C331MPFS18A-250TQC图片预览
型号: AS7C331MPFS18A-250TQC
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 1MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 21 页 / 411 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C331MPFS18A  
®
Functional description  
The AS7C331MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as  
1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.  
Fast cycle times of 4/ 4.4/ 5/ 6 ns with clock access times (t ) of 2.6/ 2.8/ 3/ 3.4 ns enable 250, 225, 200, and 166 MHz bus frequencies.  
CD  
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe  
(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.  
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register  
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data  
accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven on  
the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all  
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes  
are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count  
sequence. With LBO driven low, the device uses a linear count sequence.  
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all  
18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting  
BWE and the appropriate individual byte BWn signals.  
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when  
BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally  
to the next burst address if BWn and ADV are sampled low.  
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.  
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.  
• WEsignals are sampled on the clock edge that samples ADSC low (and ADSP high).  
Master chip enable CE0 blocks ADSP, but not ADSC.  
The AS7C331MPFS18A family operates from a core 3.3V power supply. I/ Os use a separate power supply that can operate at 2.5V or 3.3V.  
These devices are available in a 100-pin TQFP and 165-ball BGA.  
TQFP and BGA capacitance  
Parameter  
Input capacitance  
I/ O capacitance  
Symbol  
Signals  
Address and control pins  
I/ O pins  
Test conditions  
IN = 0V  
IN = V  
Max  
5
Unit  
pF  
C
V
IN  
C
V
7
pF  
I/ O  
OUT  
12/ 2/ 02, v. 0.9.2 Advance Info  
Alliance Semiconductor  
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