AS7C331MPFS18A
®
Timing characteristics over operating range
–250
–225
–200
–166
Parameter
Clock frequency
Sym Min Max Min Max Min Max Min Max Unit Notes1
fMax
tCYC
–
4
250
–
4.4
6.9
–
225
–
–
200
–
–
166 MHz
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
–
–
5
6
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYCF 6.5
–
7.5
–
–
8.5
–
tCD
tCDF
tOE
–
–
2.6
6.5
2.6
–
2.8
6.9
2.8
–
3.0
7.5
3.0
–
3.4
8.5
3.4
–
–
–
–
–
–
–
–
tLZC
tOH
0
0
0
0
2, 3, 4
2
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
–
tLZOE
tHZOE
tHZC
tOHOE
tCH
–
–
–
–
2, 3, 4
2, 3, 4
2, 3, 4
–
2.6
2.6
–
–
2.8
2.8
–
–
3.0
3.0
–
–
3.4
3.4
–
–
–
–
–
0
0
0
1.5
1.5
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
-
1.8
1.8
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
–
1.8
1.8
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
–
2.1
2.2
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
5
5
Clock low pulse width
tCL
-
–
–
–
Address setup to clock high
Data setup to clock high
tAS
-
–
–
–
6
tDS
-
–
–
–
6
Write setup to clock high
tWS
tCSS
tAH
-
–
–
–
6, 7
6, 8
6
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
-
–
–
–
-
–
–
–
tDH
-
–
–
–
6
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
tWH
tCSH
-
–
–
–
6, 7
6, 8
6
-
–
–
–
tADVS 1.2
tADSPS 1.2
tADSCS 1.2
tADVH 0.3
tADSPH 0.3
tADSCH 0.3
-
–
–
–
ADSP setup to clock high
-
–
–
–
6
ADSC setup to clock high
-
–
–
–
6
ADV hold from clock high
-
–
–
–
6
ADSP hold from clock high
ADSC hold from clock high
-
–
–
–
6
-
–
–
–
6
1 See “Notes” on page 19.
12/ 2/ 02, v. 0.9.2 Advance Info
Alliance Semiconductor
8 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
