AS7C331MPFS18A
®
Signal descriptions
Signal
CLK
I/ O Properties Description
I
I
CLOCK
SYNC
SYNC
Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
A0–A17
DQ[a,b]
I/ O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE0
CE1, CE2
ADSP
I
I
I
SYNC
SYNC
SYNC
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new bus address or to enter standby
mode.
ADSC
ADV
I
I
SYNC
SYNC
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/ write.
Global write enable. Asserted low to write all 32/ 36 and 18 bits. When high, BWE and
BW[a,b] control write enable.
GWE
BWE
I
I
SYNC
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is
low. If any of BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If
all BW[AB] are inactive, the cycle is a read cycle.
BW[a,b]
I
SYNC
Asynchronous output enable. I/ O pins are driven when OE is active and the chip is in read
mode.
OE
I
I
ASYNC
STATIC
Count mode. When driven high, count sequence follows Intel XOR convention. When
LBO
driven low, count sequence follows linear convention. This signal is internally pulled high.18
TDO
TDI
O
I
SYNC
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK
(BGA only).
TMS
TCK
FT
I
O
I
SYNC
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Flow-through mode.When low, enables single register flow-through mode. Connect to
STATIC
ASYNC
VDD if unused or for pipelined operation.
ZZ
I
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Write enable truth table (per byte)
Function
GWE
L
BWE
X
BWa
X
BWb
X
Write all bytes (a, b)
H
L
L
L
Write byte a
Write byte b
H
L
L
H
H
L
H
L
H
H
X
X
Read
H
L
H
H
ꢁꢂꢃꢄꢀX = don’t care; L = low; H = high; BWE, BWn = internal write signal
12/ 2/ 02, v. 0.9.2 Advance Info
Alliance Semiconductor
4 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
