ISL6366
Thus the total maximum power dissipated in each lower MOSFET
is approximated by the summation of P , P and
The total power dissipated by the upper MOSFET at full load can
now be approximated as the summation of the results from
Equations 34 to 39. Since the power equations depend on
MOSFET parameters, choosing the correct MOSFETs can be an
iterative process involving repetitive solutions to the loss
equations for different MOSFETs and different switching
frequencies.
LOW,1 LOW,2
P
.
LOW,3
Upper MOSFET Power Calculation
In addition to r losses, a large portion of the upper-MOSFET
DS(ON)
losses are due to currents conducted across the input voltage (V
during switching. Since a substantially higher portion of the
)
IN
upper-MOSFET losses are dependent on switching frequency, the
power calculation is more complex. Upper MOSFET losses can be
divided into separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-recovery
Current Sensing Resistor
The resistors connected to the ISEN+ pins determine the gains in
the load-line regulation loop and the channel-current balance
loop as well as setting the overcurrent trip point. Select values for
these resistors by using Equation 40:
charge, Q ; and the upper MOSFET r
conduction loss.
rr DS(ON)
When the upper MOSFET turns off, the lower MOSFET does not
conduct any portion of the inductor current until the voltage at
the phase node falls below ground. Once the lower MOSFET
R
I
OCP
N
X
(EQ. 40)
R
= --------------------------- -----------
–
ISEN
6
100 ×10
begins conducting, the current in the upper MOSFET falls to zero
as the current in the lower MOSFET ramps up to assume the full
inductor current. In Equation 34, the required time for this
where R
is the sense resistor connected to the ISEN+ pin, N
is the active channel number, R is the resistance of the current
ISEN
X
sense element, either the DCR of the inductor or R
depending on the sensing method, and I
overcurrent trip point. Typically, I
SENSE
is the desired
commutation is t and the approximated associated power loss
1
OCP
can be chosen to be 1.2
is P
.
UP,1
OCP
times the maximum load current of the specific application.
t
I
I
⎛
⎜
⎝
⎞
⎟
⎠
1
M
PP
2
(EQ. 34)
⎛
⎝
⎞
⎠
P
≈ V
F
SW
----
----- + --------
UP,1
IN
2
N
With integrated temperature compensation, the sensed current
signal is independent of the operational temperature of the
power stage, i.e. the temperature effect on the current sense
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t . In Equation 35, the approximate
2
element R is cancelled by the integrated temperature
X
power loss is P
.
UP,2
compensation function. R in Equation 40 should be the
X
I
t
2
⎛I
⎞ ⎛
⎞
⎟
⎠
(EQ. 35)
PP
2
M
N
resistance of the current sense element at the room
temperature.
P
≈ V
F
SW
-------- ----
⎟ ⎜
⎜
⎝
----- –
UP,2
IN
2
⎠ ⎝
When the integrated temperature compensation function is
disabled by selecting “OFF” TCOMP code, the sensed current will
be dependent on the operational temperature of the power
stage, since the DC resistance of the current sense element may
A third component involves the lower MOSFET’s reverse-recovery
charge, Q . Since the inductor current has fully commutated to the
rr
upper MOSFET before the lower-MOSFET’s body diode can draw all
of Q , it is conducted through the upper MOSFET across VIN. The
rr
be changed according to the operational temperature. R in
power dissipated as a result is P
Equation 36:
and is approximated in
X
UP,3
Equation 40 should be the maximum DC resistance of the
current sense element at the all operational temperature.
(EQ. 36)
P
= V
Q F
UP,3
IN rr SW
In certain circumstances, especially for a design with an
unsymmetrical layout, it may be necessary to adjust the value of
one or more ISEN resistors for VR0. When the components of one
or more channels are inhibited from effectively dissipating their
heat so that the affected channels run cooler than the average,
The resistive part of the upper MOSFET’s is given in Equation 37
as P
.
UP,4
2
2
⎛
⎜
⎝
⎞
⎟
⎠
I
PP
I
(EQ. 37)
M
P
≈ r
+
⋅ d
---------
12
-----
UP,4
DS(ON)
choose new, larger values of R
for the affected phases (see
N
ISEN
the section entitled “Current Sensing” on page 17). Choose
in proportion to the desired increase in temperature rise
R
Equation 38 accounts for some power loss due to the drain-
ISEN,2
in order to cause proportionally more current to flow in the cooler
phase, as shown in Equation 41:
source parasitic inductance (L , including PCB parasitic
DS
inductance) of the upper MOSFETs, although it is not the exact:
2
ΔT
2
⎛
⎜
⎝
I
⎞
⎟
⎠
I
R
= R
= R
----------
PP
2
M
ISEN,2
ISEN
(EQ. 38)
P
≈ L
+
--------
-----
ΔT
(EQ. 41)
UP,5
DS
1
N
ΔR
– R
ISEN
ISEN
ISEN,2
Finally, the power loss of output capacitance of the upper
MOSFET is approximated in Equation 39:
In Equation 41, make sure that ΔT is the desired temperature rise
2
above the ambient temperature, and ΔT is the measured
temperature rise above the ambient temperature. Since all
1
2
3
1.5
(EQ. 39)
--
P
≈
⋅ V
⋅ C
⋅
V
⋅ F
DS_UP SW
UP,6
IN
OSS_UP
channels’ R
are integrated and set by one RSET, a resistor
ISEN
(ΔR
) should be in series with the cooler channel’s ISEN+ pin
ISEN
where C
is the output capacitance of lower MOSFET at
test voltage of V . Depending on the amount of ringing, the
OSS_UP
to raise this phase current. While a single adjustment according to
Equation 41 is usually sufficient, it may occasionally be necessary
DS_UP
actual power dissipation will be slightly higher than this.
FN6964.0
January 3, 2011
36
INTERSIL [ Intersil ]
