HS-3282
CLK
37
RCV CLK
RCVSEL
WDCNT 1
WORD GAP
TXSEL
DATA CLOCK
DATA S/R 1
32
LATCH 1
16
16
S/D
DECODER
WDCNT 1
WDCNT 2
16
16
SEL 2
16
D
F/F
LATCH 2
4
LINE
RECEIV.
ER 2
32
SEL
SELF
TEST
WLSEL
RCV CLK
39
6
7
8
9
10
BD15-
BD00
DATA
BUS
28
29
30
DATA S/R 2
DATA CLOCK
WORD GAP
WDCNT 2
22 - 27
PARCK
SELF
TEST
16
16
16
32
31
429D0
SEL EN2
D
F/F
TX CLK
WLSEL
SEL 1
SEL EN1
11
16
RCV
TIMING
CONTROL
WORD
REGISTER
TX
TX CLK
38
V
CC
1
GND
21
SLF TST
(BD05)
S/D ENB1
(BD06)
S/D ENB2
(BD09)
X1 (BD07)
Y1 (BD06)
X2 (BD10)
Y2 (BD11)
PARCK
(BD12)
TXSEL
(BD13)
RCVSEL
(BD14)
WLSEL
(BD15)
34
CWSTR
WLSEL
SELF
TEST
429D11 (A)
2
LINE
RECEIV.
ER 1
SLF
TEST
S/DENB
SEL
429D11 (B)
RCV
CLK
TX
CLK
3
S/D CODER
429D12 (A)
TX WORD
GAP
33
ENTX
429D12 (B)
5
FIFO
8 x 31
PARITY
TXC
DRVR
429D0
11 - 20
MR
D/R1 D/R2
SEL EN1 EN2
PL1 PL2
TX/R
FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM
5-190
INTERSIL [ INTERSIL CORPORATION ]
