HS-3282
Timing Waveforms
TX/R
TX ENABLE
DATA BUS
PL1
PL2
D/R1
D/R2
EN1
EN2
SEL
TIME
INTERVAL A
TIME
INTERVAL B
TIME
INTERVAL C
TIME
INTERVAL D
TIME
INTERVAL E
BUS IS BEING USED AS AN OUTPUT
BUS IS BEING USED AS AN INPUT
FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE
429DI
D/R
BIT
32
t
t
END/R
D/R
t
t
ENEN
D/REN
EN
t
SELEN
t
t
t
ENSEL
SELEN
ENSEL
t
EN
t
EN
SEL
t
t
ENDATA
DATAEN
t
t
DATAEN
ENDATA
BD00-15
WORD
1
WORD
2
OR
SEL
WORD
2
WORD
1
BD00-15
FIGURE 3. RECEIVER TIMING
t
CWSTR
CWSTR
BD00-15
t
CWHLD
t
CWSET
CONTROL WORD
FIGURE 4. CONTROL WORD TIMING
5-194