HS-3282
Operational Description
The HS-3282 is designed to support ARINC Specification
429 and other serial data protocols that use a similar format
by collecting the receiving, transmitting, synchronizing,
timing and parity functions on a single, low power LSl circuit.
It goes beyond the ARlNC requirements by providing for
either odd or even parity, and giving the user a choice of
either 25 or 32-bit word lengths. The receiver and transmitter
sections operate independently of each other. The serial-to-
parallel conversion required of the receiver and the parallel-
to-serial conversion requirements of the transmitter have
been incorporated into the bus interface circuit.
Provisions have been made through the external clock input
to provide data rate flexibility. This requires an external clock
that is 10 times the data rate.
To obtain the flexibility discussed above, a number of
external control signals are required, To reduce the pin count
requirements, an internal control word register is used. The
control word is latched from the data bus into the register by
the Control Word Strobe (CWSTR) signal going to a logic
“1”. Eleven (11) control functions are used, and along with
the Bus Data (BD) line are listed below:
Control Word
PIN NAME
BD05
SYMBOL
SLFTST
FUNCTION
Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input
receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output
remains active. (Logic “0” on SLFTST Enables Self Test).
Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder).
If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be
accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
If SDENBI = “1” then this bit is compared with ARINC Data Bit #10. If X1 also matches (see X1), the word will
be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder).
If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be
accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will
be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
Signal used to invert the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity. Logic
“I” selects even parity.
Selects high or low Transmitter data rate. If TXSEL = “0” then transmitter data rate is equal to the clock rate
divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80).
Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock
rate divided by ten (10), if RCVSEL = “1 “then the received data rate should be equal to the clock rate divided
by eighty (80).
Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format
will be selected.
BD06
BD07
BD08
BD09
BD10
BD11
BD12
BD13
BD14
SDENB1
X1
Y1
SDENB2
X2
Y2
PARCK
TXSEL
RCVSEL
BD15
WLSEL
ARlNC 429 DATA FORMAT as input to the Receiver and out-
put from the Transmitter is as follows:
TABLE 1. ARINC 429 32-BIT DATA FORMAT
ARINC BIT #
1-8
9 - 10
11
12 - 27
28
29
30, 31
32
FUNCTION
Label
SDl or Data
LSB
Data
MSB
Sign
SSM
Parity Status
This format is shuffled when seen on the sixteen bidirec-
tional input/outputs. The format shown below is used from
the receivers and input to the transmitter:
TABLE 2A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT #
15, 14
13
12, 11
10, 9
8
7 - 00
FUNCTION
Data
LSB
SDl or Data
SSM Status
Parity Status
Label
ARINC BlT #
13, 12
11
10, 9
31, 30
32
1-8
5-187
INTERSIL [ INTERSIL CORPORATION ]
