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5962-8688001QA 参数 Datasheet PDF下载

5962-8688001QA图片预览
型号: 5962-8688001QA
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ARINC总线接口电路 [CMOS ARINC Bus Interface Circuit]
分类和应用:
文件页数/大小: 15 页 / 179 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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HS-3282
Pin Description
PIN
31
32
33
34
SYMBOL
429D0
429D0
ENTX
CWSTR
(Continued)
SECTION
Transmitter
Transmitter
Transmitter
Recs/Trans
Data output from Transmitter
Data output from Transmitter.
Transmitter Enable input signal to initiate data transmission from FIFO memory.
Control word input strobe signal to latch the control word from the databus into the control
word register.
No connection. Must be left open.
No connection. Must be left open or tied low but never tied high.
External clock input. May be either ten (10) or eighty (80) times the data rate. If using both
ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz).
Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate.
Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal,
TX/R and various other flags and controls. Master reset does not reset the control word
register. Usually only used on Power-Up or System Reset.
No Connection.
DESCRIPTION
35
36
37
-
-
CLK
-
-
Recs/Trans
38
39
TXCLK
MR
Transmitter
Recs/Trans
40
-
-
Pinout
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC NC
NC
5-186