28F640L30, 28F128L30, 28F256L30
Refer to Table 8, “LC and Frequency Support for Bin 1 tAVQV/tCHQV (85ns / 17ns)” on page 25
and Table 9, “LC and Frequency Support for Bin 2 tAVQV/tCHQV (110ns / 20ns)” on page 26 for
Latency Code Settings.
Figure 4. First-Access Latency Count
CLK [C]
Address [A]
ADV# [V]
Valid
Address
Code 0 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1
(Reserved
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
Code 4
Code 5
Code 6
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Table 8. LC and Frequency Support for Bin 1 tAVQV/tCHQV (85ns / 17ns)
Latency Count Settings
Frequency Support (MHz)
2
≤ 27
≤ 40
≤ 52
3
4, 5, 6, or 7
Datasheet
25
INTEL [ INTEL ]
