28F640L30, 28F128L30, 28F256L30
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see Section 4.3.2, “Latency
Count” on page 24). Subsequent data is output on valid CLK edges following a minimum delay.
However, for a synchronous non-array read, the same word of data will be output on successive
clock edges until the burst length requirements are satisfied.
During synchronous read operations, WAIT is driven with respect to OE# assertion. WAIT
indicates invalid data when asserted, and valid data when de-asserted with respect to a valid clock
edge. See Figure 16 through Figure 18 for additional details.
4.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred
when system software needs to suspend a burst sequence that is in progress in order to retrieve data
from another device on the same system bus. The system processor can resume the burst sequence
later. Burst suspend provides maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is received) or after
the device has output data. When a burst access is suspended, internal array sensing continues and
any previously latched internal data is retained. A burst sequence can be suspended and resumed
without limit as long as device operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL. WAIT is in High-Z during OE# de-assertion.
To resume the burst access, OE# is reasserted, and CLK is restarted. Subsequent CLK edges
resume the burst sequence.
Within the device, CE# and OE# gate WAIT. Therefore, during Burst Suspend WAIT is placed in
high-impedance state when OE# is de-asserted and resumed active when OE# is re-asserted. See
Figure 19, “Burst Suspend Timing” on page 59.
4.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines the
synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read
Configuration Register command (see Section 3.2, “Device Commands” on page 18).
RCR contents can be examined using the Read Device Identifier command, and then reading from
<partition base address> + 0x05 (see Section 9.2, “Read Device Identifier” on page 48).
The RCR is shown in Table 7. The following sections describe each RCR bit.
Table 7. Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Data WAIT
Hold Delay
Burst
Wrap
Read
Mode
WAIT
Burst
Seq
CLK
RES
Latency Count
LC[2:0]
RES RES
Burst Length
Polarity
Edge
RM
15
R
WP
10
DH
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Bit
Name
Description
Datasheet
23
INTEL [ INTEL ]
